MOS transistors, such as e.g. MOSFETs or IGBTs, can be used as electronic switches for switching electrical loads. Such MOS transistors suitable for switching electrical loads are also referred to as power MOS transistors. One aim in the development of these MOS transistors is to achieve a lowest possible area-specific on resistance (RON·A) for a given dielectric strength. This area-specific on resistance is the product of the ohmic resistance (RON) of the transistor in the on state and the chip area (A) required for realizing the transistor.
Power transistors have a drift zone, in which a space charge zone or depletion layer zone can propagate when the component is turned off and a reverse voltage is present, and which in this way takes up the reverse voltage present. In the case of compensation components, a complementarily doped compensation zone is present in the drift zone, wherein the drift zone and the compensation zone are mutually depleted of charge carriers when the component is turned off. The provision of such a compensation zone permits a higher doping of the drift zone for the same dielectric strength. Relative to the on resistivity, this means that the on resistance (RON) can be reduced with the chip area (A) remaining the same, or that the chip area can be reduced with the on resistance remaining the same.
With reduction of the chip area and the associated reduction of the capacitances contained in the component, the switching behavior of the transistor changes to the effect that the transistor switches more rapidly, that is to say that when suitable drive signals are applied to a gate electrode, the transistor changes more rapidly from the on state to the off state or from the off state to the on state. Rapid switching is tantamount to steep edges of a voltage present across the transistor or the switched load or of a current flowing through the transistor and the load. Both steep voltage edges and steep current edges can be critical with regard to radiated electromagnetic interference. Furthermore, steep current edges in parasitic inductances can lead to high voltage spikes, and steep voltage edges in conjunction with parasitic capacitances can lead to undesirable oscillations.